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1 ltc1735 1735fc high efficiency synchronous step-down switching regulator the ltc ? 1735 is a synchronous step-down switching regulator controller that drives external n-channel power mosfets using a fixed frequency architecture. burst mode tm operation provides high efficiency at low load currents. the precision 0.8v reference is compatible with future generation microprocessors. opti-loop compen- sation allows the transient response to be optimized over a wide range of output capacitance and esr values. the operating frequency (synchronizable up to 500khz) is set by an external capacitor allowing maximum flexibility in optimizing efficiency. a forced continuous control pin reduces noise and rf interference and can assist second- ary winding regulation by disabling burst mode operation when the main output is lightly loaded. protection features include internal foldback current lim- iting, output overvoltage crowbar and optional short- circuit shutdown. soft-start is provided by an external capacitor that can be used to properly sequence supplies. the operating current level is user-programmable via an external current sense resistor. wide input supply range allows operation from 4v to 30v (36v maximum). n synchronizable/programmable fixed frequency n opti-loop tm compensation minimizes c out n 1% output voltage accuracy n dual n-channel mosfet synchronous drive n wide v in range: 4v to 36v operation n v out range: 0.8v to 6v n internal current foldback n output overvoltage crowbar protection n latched short-circuit shutdown timer with defeat option n very low dropout operation: 99% duty cycle n forced continuous control pin n optional programmable soft-start n remote output voltage sense n power good output (ltc1735f only) n logic controlled micropower shutdown: i q < 25 m a n ltc1435 pin compatible with minor component changes n available in 16-lead narrow ssop, so packages and 20-lead tssop package (ltc1735f only) figure 1. high efficiency step-down converter , ltc and lt are registered trademarks of linear technology corporation. burst mode and opti-loop are trademarks of linear technology corporation. n notebook and palmtop computers, pdas n cellular telephones and wireless modems n dc power distribution systems c osc run/ss tg boost ltc1735 c b 0.22 f 100pf c c 330pf r c 33k r sense 0.005 v out 1.6v 9a c out : panasonic eefueog181r c in : marcon thcr70e1h226zt l1: panasonic etqp6f2r0hfa r sense : irc lrf2010-01-r005j 1000pf c ss 0.1 f c osc 47pf + 4.7 f + c out 180 f 4v 4 sp c in 22 f 50v m1 fds6680a m2 fds6680a 1735 f01 d b cmdsh-3 d1 mbrs340t3 v in 5v to 24v l1 2 h c c2 100pf r2 20k 1% r1 20k 1% sgnd v osense sense sense + intv cc bg pgnd i th sw v in features descriptio u applicatio s u typical applicatio u
2 ltc1735 1735fc absolute axi u rati gs w ww u input supply voltage (v in ).........................36v to C 0.3v topside driver supply voltage (boost)....42v to C 0.3v switch voltage (sw) ....................................36v to C 5v extv cc voltage ...........................................7v to C 0.3v boosted driver voltage (boost C sw) .......7v to C 0.3v sense + , sense C voltages .......... 1.1 (intv cc ) to C 0.3v fcb voltage ............................(intv cc + 0.3v) to C 0.3v i th , v osense voltages ............................... 2.7v to C 0.3v run/ss, pgood (ltc1735f only) voltages .......................................................7v to C 0.3v electrical characteristics the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 15v, v run/ss = 5v unless otherwise noted. peak driver output current <10 m s (tg, bg) .............. 3a intv cc output current ......................................... 50ma operating ambient temperature range ltc1735c ............................................... 0 c to 85 c ltc1735i/ltc1735e (note 8) ............ C 40 c to 85 c junction temperature (note 2) ............................. 125 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c (note 1) package/order i for atio uu w order part number ltc1735cgn ltc1735cs ltc1735ign ltc1735is ltc1735egn t jmax = 125 c, q ja = 130 c/w (gn) t jmax = 125 c, q ja = 110 c/w (s) top view s package 16-lead plastic so gn package 16-lead narrow plastic ssop 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 c osc run/ss i th fcb sgnd v osense sense sense + tg boost sw v in intv cc bg pgnd extv cc gn part marking 1735 1735i 1735e consult ltc marketing for parts specified with wider operating temperature ranges. order part number ltc1735cf ltc1735if t jmax = 125 c, q ja = 110 c/w 1 2 3 4 5 6 7 8 9 10 top view f package 20-lead plastic tssop 20 19 18 17 16 15 14 13 12 11 nc c osc run/ss i th fcb sgnd v osense pgood sense sense + nc tg boost sw v in intv cc bg pgnd extv cc nc symbol parameter conditions min typ max units main control loop i vosense feedback current (note 3) C 4 C 25 na v osense feedback voltage (note 3) l 0.792 0.8 0.808 v d v linereg reference voltage line regulation v in = 3.6v to 30v (note 3) 0.001 0.02 %/v d v loadreg output voltage load regulation (note 3) measured in servo loop; v ith = 0.7v l 0.1 0.3 % measured in servo loop; v ith = 2v l C 0.1 C 0.3 % df max maximum duty factor in dropout 98 99.4 % g m transconductance amplifier g m 1.3 mmho v fcb forced continuous threshold l 0.76 0.8 0.84 v i fcb forced continuous current v fcb = 0.85v C 0.17 C 0.3 m a
3 ltc1735 1735fc symbol parameter conditions min typ max units electrical characteristics the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 15v, v run/ss = 5v unless otherwise noted. v ovl feedback overvoltage lockout l 0.84 0.86 0.88 v i q input dc supply current (note 4) normal mode 450 m a shutdown v run/ss = 0v 15 25 m a v run/ss run pin start threshold v run/ss , ramping positive 1.0 1.5 1.9 v v run/ss run pin begin latchoff threshold v run/ss , ramping positive 4.1 4.5 v i run/ss soft-start charge current v run/ss = 0v C 0.7 C 1.2 m a i scl run/ss discharge current soft short condition, v osense = 0.5v, 0.5 2 4 m a v run/ss = 4.5v uvlo undervoltage lockout measured at v in pin (v in ramping down) l 3.5 3.9 v d v sense(max) maximum current sense threshold v osense = 0.7v l 60 75 85 mv i sense sense pins total source current v sense C = v sense + = 0v 60 80 m a t on(min) minimum on-time tested with a square wave (note 6) 160 200 ns tg transition time: (note 7) tg t r rise time c load = 3300pf 50 90 ns tg t f fall time c load = 3300pf 50 90 ns bg transition time: (note 7) bg t r rise time c load = 3300pf 50 90 ns bg t f fall time c load = 3300pf 40 80 ns tg/bg t 1d top gate off to synchronous c load = 3300pf each driver 100 ns gate on delay time tg/bg t 2d synchronous gate off to top c load = 3300pf each driver 70 ns gate on delay time internal v cc regulator v intvcc internal v cc voltage 6v < v in < 30v, v extvcc = 4v 5.0 5.2 5.4 v v ldo(int) internal v cc load regulation i cc = 0 to 20ma, v extvcc = 4v 0.2 1 % v ldo(ext) extv cc drop voltage i cc = 20ma, v extvcc = 5v 130 200 mv v extvcc extv cc switchover voltage i cc = 20ma, extv cc ramping positive l 4.5 4.7 v v extvcc(hys) extv cc hysteresis 0.2 v oscillator f osc oscillator frequency c osc = 43pf (note 5) 265 300 335 khz f h /f osc maximum sync frequency ratio 1.3 f fcb(sync) fcb pin threshold for sync ramping negative 0.9 1.2 v pgood output (ltc1735f only) v pgl pgood voltage low i pgood = 2ma 110 200 mv i pgood pgood leakage current v pgood = 5v 1 m a v pg pgood trip level v osense with respect to set output voltage v osense ramping negative C 6.0 C 7.5 C 9.5 % v osense ramping positive 6.0 7.5 9.5 % note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formulas: ltc1735cs, ltc1735is: t j = t a + (p d ? 110 c/w) ltc1735cgn, ltc1735ign, ltc1735egn: t j = t a + (p d ? 130 c/w) ltc1735cf, ltc1735if: t j = t a + (p d ? 110 c/w)
4 ltc1735 1735fc typical perfor a ce characteristics uw efficiency vs load current (3 operating modes) efficiency vs load current efficiency vs input voltage load current (a) 0.001 efficiency (%) 60 70 80 burst sync 10 1735 g01 50 40 20 0.01 0.1 1 30 100 90 v in = 10v v out = 3.3v r s = 0.01 f o = 300khz extv cc open continuous load current (a) 0.01 0.1 1 10 efficiency (%) 1735 g02 100 90 80 70 60 50 40 v in = 5v extv cc = 5v figure 1 v in = 24v v in = 15v input voltage (v) 0 70 efficiency (%) 75 80 85 90 100 5 10 15 20 1735 g03 25 30 95 extv cc = 5v v out = 1.6v figure 1 i out = 5a i out = 0.5a efficiency vs input voltage load regulation v in C v out dropout voltage vs load current input voltage (v) 0 70 efficiency (%) 75 80 85 90 100 5 10 15 20 1735 g04 25 30 95 extv cc open v out = 1.6v figure 1 i out = 5a i out = 0.5a load current (a) 0 normalized v out (%) 0.2 0.1 8 1735 g05 0.3 0.4 2 4 6 10 0 fcb = 0v v in = 15v figure 1 load current (a) 0 0 v in ?v out (mv) 500 400 300 200 100 2468 1735 g06 10 r sense = 0.005 v out = 5v ?5% drop note 3: the ltc1735 is tested in a feedback loop that servos v osense to the balance point for the error amplifier (v ith = 1.2v). note 4: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 5: oscillator frequency is tested by measuring the c osc charge current (i osc ) and applying the formula: f cpf i i osc osc chg dis = + ? ? ? ? + ? ? ? ? 8 477 10 11 11 11 1 .() () note 6: the minimum on-time condition corresponds to an inductor peak- to-peak ripple current 3 40% of i max (see minimum on-time considerations in the applications information section). note 7: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. note 8: the ltc1735e is guaranteed to meet performance specifications from 0 c to 85 c. specifications over the C40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltc1735i specifications are guaranteed over the full C40 c to 85 c operating temperature range. electrical characteristics
5 ltc1735 1735fc maximum current sense threshold vs normalized output voltage (foldback) typical perfor a ce characteristics uw maximum current sense threshold vs v run/ss maximum current sense threshold vs sense common mode voltage maximum current sense threshold vs i th voltage v ith vs v run/ss maximum current sense threshold vs temperature normalized output voltage (%) 0 maximum current sense threshold (mv) 40 50 60 100 1735 g10 30 20 0 25 50 75 10 80 70 v run/ss (v) 0 0 maximum current sense threshold (mv) 20 40 60 80 1234 1735 g11 56 v sense(cm) = 1.6v common mode voltage (v) 0 maximum current sense threshold (mv) 72 76 80 4 1735 g12 68 64 60 1 2 3 5 v ith (v) 0 maximum current sense threshold (mv) 30 50 70 90 2 1735 g13 10 ?0 20 40 60 80 0 ?0 ?0 0.5 1 1.5 2.5 v run/ss (v) 0 0 v ith (v) 0.5 1.0 1.5 2.0 2.5 1 234 1735 g15 56 v osense = 0.7v temperature ( c) ?0 60 maximum current sense threshold (mv) 65 70 75 80 ?5 10 35 60 1735 g18 85 110 135 v sense(cm) = 1.6v input and shutdown currents vs input voltage intv cc line regulation input voltage (v) 05 0 input current ( a) shutdown current ( a) 200 500 10 20 25 1735 g07 100 400 300 0 40 100 20 80 60 15 30 35 extv cc open shutdown extv cc = 5v input voltage (v) 0 intv cc voltage (v) 4 5 6 15 25 1735 g08 3 2 510 20 30 35 1 0 1ma load extv cc switch drop vs intv cc load current intv cc load current (ma) 0 extv cc ?intv cc (mv) 300 400 500 40 1735 g09 200 100 0 10 20 30 50
6 ltc1735 1735fc typical perfor a ce characteristics uw oscillator frequency vs temperature temperature ( c) ?0 ?5 250 frequency (khz) 270 300 10 60 85 1735 g19 260 290 280 35 110 135 c osc = 47pf run/ss pin current vs temperature temperature ( c) 40 ?5 ? run/ss current ( a) ? 0 10 60 85 1735 g20 ? ? ? 35 110 135 v run/ss = 0v temperature ( c) 40 ?5 ?.0 fcb current ( a) 0.6 0 10 60 85 1735 g21 0.8 0.2 0.4 35 110 135 v fcb = 0.85v fcb pin current vs temperature output current vs duty cycle sense pins total source current i th voltage vs load current duty cycle (%) 0 0 average output current i out /i max (%) 20 40 60 80 100 20 40 60 80 1735 g14 100 f sync = f o i out /i max (sync) i out /i max (free run) v sense common mode voltage (v) 0 i sense ( a) 0 1735 g16 ?0 100 24 50 100 6 load current (a) 0 0 i th voltage (v) 0.5 1.0 1.5 2.0 2.5 1 234 1735 g17 56 v in = 10v v out = 3.3v r sense = 0.01 f o = 300khz continuous mode burst mode operation synchronized f = f o supply current in shutdown vs v run/ss v run/ss 0 0 supply current ( a) 10 30 40 50 100 70 0.5 1 1735 g28 20 80 90 60 1.5 2 temperature ( c) ?0 0 supply current ( a) 5 10 15 20 25 30 0 50 100 150 1735 g29 supply current in shutdown vs temperature
7 ltc1735 1735fc pi fu ctio s uuu v out(ripple) (burst mode operation) load step (burst mode operation) load step (continuous mode) v out 50mv/div i l 5a/div 0a to 10 m s/div 9a load step fcb = 0v v in = 15v v out = 1.6v v out 50mv/div i l 5a/div v out 20mv/div i l 5a/div fcb = 5v 5 m s/div v in = 15v v out = 1.6v 10ma to 10 m s/div 9a load step fcb = 5v v in = 15v v out = 1.6v 1735 g27 1735 g26 1735 g25 figure 1 figure 1 figure 1 i load = 1.5a typical perfor a ce characteristics uw start-up v out 1v/div v run/ss 5v/div i l 5a/div v in = 15v 5ms/div v out = 1.6v r load = 0.16 w v out(ripple) (synchronized) v out 10mv/div i l 5a/div ext sync f = f o 10 m s/div v in = 15v v out = 1.6v v out 20mv/div i l 5a/div v out(ripple) (burst mode operation) fcb = 5v 50 m s/div v in = 15v v out = 1.6v 1735 g22 1735 g23 1735 g24 figure 1 figure 1 i load = 10ma i load = 50ma c osc : external capacitor c osc from this pin to ground sets the operating frequency. run/ss: combination of soft-start and run control in- puts. a capacitor to ground at this pin sets the ramp time to full output current. the time is approximately 1.25s/ m f. forcing this pin below 1.5v causes the device to shut down. (see applications information section for quiescent current note.) in shutdown all functions, including intv cc , are disabled. latchoff overcurrent protection is also in- voked via this pin as described in the applications infor- mation section. i th : error amplifier compensation point. the current comparator threshold increases with this control voltage. nominal voltage range for this pin is 0v to 2.4v. fcb: forced continuous/synchronization input. tie this pin to ground for continuous synchronous operation, to a resistive divider from the secondary output when using a secondary winding or to intv cc to enable burst mode operation at low load currents. clocking this pin with a signal above 1.5v pCp disables burst mode operation but allows cycle-skipping at low load currents and synchro- nizes the internal oscillator with the external clock. the fcb pin must not be driven when the device is shut down (run/ss pin low). sgnd: small-signal ground. all small-signal components such as c osc , c ss , the feedback divider plus the loop com- pensation resistor and capacitor(s) should single-point tie to this pin. this pin should, in turn, connect to pgnd.
8 ltc1735 1735fc v osense : receives the feedback voltage from an external resistive divider across the output. sense C : the (C) input to the current comparator. sense + : the (+) input to the current comparator. built-in offsets between sense C and sense + pins in conjunction with r sense set the current trip threshold. pgood (ltc1735f only): open-drain logic output. pgood is pulled to ground when the voltage on the v osense pin is not within 7.5% of its set point. extv cc : input to the internal switch connected to intv cc . this switch closes and supplies v cc power whenever extv cc is higher than 4.7v. see extv cc connection in the applications information section. do not exceed 7v on this pin and ensure extv cc v in . pgnd: driver power ground. connects to the source of bottom n-channel mosfet, the anode of the schottky diode, and the (C) terminal of c in . bg: high current gate drive for bottom n-channel mosfet. voltage swing at this pin is from ground to intv cc . intv cc : output of the internal 5.2v regulator and extv cc switch. the driver and control circuits are powered from this voltage. decouple to power ground with a 1 m f ceramic capacitor placed directly adjacent to the ic together with a minimum of 4.7 m f tantalum or other low esr capacitor. v in : main supply pin. must be closely decoupled to power ground. sw: switch node connection to inductor and bootstrap capacitor. voltage swing at this pin is from a schottky diode (external) voltage drop below ground to v in . boost: supply to topside floating driver. the bootstrap capacitor is returned to this pin. voltage swing at this pin is from a diode drop below intv cc to (v in + intv cc ). tg: high current gate drive for top n-channel mosfet. this is the output of a floating driver with a voltage swing equal to intv cc superimposed on the switch node voltage sw. pi fu ctio s uuu
9 ltc1735 1735fc fu ctio al diagra uu w sw + + 0.86v + 0.55v 2.4v 0.8v 0.86v i 1 + i 2 + ea a burst disable fc ov gm =1.3m b + 4.7v irev + + f fc s r q drop out det 0.8v ref switch logic sd 6v r1 run/ss c ss r c v osense v fb 1.2 a run soft- start + over- current latchoff sd i th c c 0.17 a osc 4(v fb ) buffered i th slope comp + + 3mv icmp r2 2k 45k bot top on force bot 45k 30k 30k sense + sense sync 1.2v 0.8v c top uvl bot intv cc 5.2v ldo reg v in + c intvcc v out v sec intv cc bg pgnd v in v in boost tg intv cc c b d b d 1 c osc + c in + c sec + c out extv cc fcb sgnd c osc r sense 1735 fd pgood ltc1735f only + 0.74v operatio u (refer to functional diagram) main control loop the ltc1735 uses a constant frequency, current mode step-down architecture. during normal operation, the top mosfet is turned on each cycle when the oscillator sets the rs latch and turned off when the main current comparator i 1 resets the rs latch. the peak inductor current at which i 1 resets the rs latch is controlled by the voltage on pin 3 (i th ), which is the output of error amplifier ea. pin 6 (v osense ), described in the pin func- tions, allows ea to receive an output feedback voltage v fb from an external resistive divider. when the load current increases, it causes a slight decrease in v fb relative to the 0.8v refer ence, which in turn causes the i th voltage to increase until the average inductor current matches the new load current. while the top mosfet is off, the bottom mosfet is turned on until either the inductor current starts to reverse, as indicated by current comparator i 2 , or the beginning of the next cycle. the top mosfet driver is powered from a floating boot- strap capacitor c b . this capacitor is normally recharged from intv cc through an external diode when the top mosfet is turned off. as v in decreases towards v out , the converter will attempt to turn on the top mosfet continu- ously (dropout). a dropout counter detects this condi- tion and forces the top mosfet to turn off for about 500ns every tenth cycle to recharge the bootstrap capacitor.
10 ltc1735 1735fc operatio u (refer to functional diagram) when the fcb pin is driven by an external oscillator, a low noise cycle-skipping mode is invoked and the internal oscillator is synchronized to the external clock by com- parator c. in this mode the 25% minimum inductor current clamp is removed, providing constant frequency discontinuous operation over the widest possible output current range. this constant frequency operation is not quite as efficient as burst mode operation, but provides a lower noise, constant frequency spectrum. tying the fcb pin to ground enables forced continuous operation. this is the least efficient mode, but is desirable in certain applications. the output can source or sink current in this mode. when sinking current while in forced continuous operation, current will be forced back into the main power supply potentially boosting the input supply to dangerous voltage levelsbeware. foldback current, short-circuit detection and short-circuit latchoff the run/ss capacitor, c ss , is used initially to limit the inrush current of the switching regulator. after the con- troller has been started and been given adequate time to charge up the output capacitors and provide full load cur- rent, c ss is used as a short-circuit time-out circuit. if the output voltage falls to less than 70% of its nominal output voltage, c ss begins discharging on the assumption that the output is in an overcurrent and/or short-circuit condi- tion. if the condition lasts for a long enough period as determined by the size of c ss , the controller will be shut down until the run/ss pin voltage is recycled. this built- in latchoff can be overridden by providing a current >5 m a at a compliance of 5v to the run/ss pin. this current shortens the soft-start period but also prevents net dis- charge of c ss during an overcurrent and/or short-circuit condition. foldback current limiting is activated when the output voltage falls below 70% of its nominal level whether or not the short-circuit latchoff circuit is enabled. the main control loop is shut down by pulling pin 2 (run/ss) low. releasing run/ss allows an internal 1.2 m a current source to charge soft-start capacitor c ss . when c ss reaches 1.5v, the main control loop is enabled with the i th voltage clamped at approximately 30% of its maximum value. as c ss continues to charge, i th is gradually re- leased allowing normal operation to resume. if v out has not reached 70% of its final value when c ss has charged to 4.1v, latchoff can be invoked as described in the applications information section. the internal oscillator can be synchronized to an external clock applied to the fcb pin and can lock to a frequency between 90% and 130% of its nominal rate set by capaci- tor c osc . an overvoltage comparator, ov, guards against transient overshoots (>7.5%) as well as other more serious conditions that may overvoltage the output. in this case, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. foldback current limiting for an output shorted to ground is provided by amplifier a. as v osense drops below 0.6v, the buffered i th input to the current comparator is gradu- ally pulled down to a 0.86v clamp. this reduces peak inductor current to about 1/4 of its maximum value. low current operation the ltc1735 has three low current modes controlled by the fcb pin. burst mode operation is selected when the fcb pin is above 0.8v (typically tied to intv cc ). in burst mode operation, if the error amplifier drives the i th voltage below 0.86v, the buffered i th input to the current com- parator will be clamped at 0.86v. the inductor current peak is then held at approximately 20mv/r sense (about 1/4 of maximum output current). if i th then drops below 0.5v, the burst mode comparator b will turn off both mosfets to maximize efficiency. the load current will be supplied solely by the output capacitor until i th rises above the 60mv hysteresis of the comparator and switch- ing is resumed. burst mode operation is disabled by comparator f when the fcb pin is brought below 0.8v. this forces continuous operation and can assist second- ary winding regulation.
11 ltc1735 1735fc intv cc /extv cc power power for the top and bottom mosfet drivers and most of the internal circuitry of the ltc1735 is derived from the intv cc pin. when the extv cc pin is left open, an internal 5.2v low dropout regulator supplies the intv cc power from v in . if extv cc is raised above 4.7v, the internal regulator is turned off and an internal switch connects extv cc to intv cc . this allows a high efficiency source, such as the primary or a secondary output of the converter itself, to provide the intv cc power. voltages up to 7v can be applied to extv cc for additional gate drive capability. to provide clean start-up and to protect the mosfets, undervoltage lockout is used to keep both mosfets off until the input voltage is above 3.5v. pgood (ltc1735f only) a window comparator monitors the output voltage and its open-drain output is pulled low when the divided down output voltage is not within 7.5% of the reference voltage of 0.8v. operatio u (refer to functional diagram) applicatio s i for atio wu u u the basic ltc1735 application circuit is shown in figure 1 on the first page. external component selection is driven by the load requirement and begins with the selection of r sense . once r sense is known, c osc and l can be chosen. next, the power mosfets and d1 are selected. the operating frequency and the inductor are chosen based largely on the desired amount of ripple current. finally, c in is selected for its ability to handle the large rms current into the converter and c out is chosen with low enough esr to meet the output voltage ripple and transient speci- fications. the circuit shown in figure 1 can be configured for operation up to an input voltage of 28v (limited by the external mosfets). r sense selection for output current r sense is chosen based on the required output current. the ltc1735 current comparator has a maximum thresh- old of 75mv/r sense and an input common mode range of sgnd to 1.1(intv cc ). the current comparator threshold sets the peak of the inductor current, yielding a maximum average output current i max equal to the peak value less half the peak-to-peak ripple current, d i l . allowing a margin for variations in the ltc1735 and external component values yields: r mv i sense max = 50 c osc selection for operating frequency and synchronization the choice of operating frequency and inductor value is a trade-off between efficiency and component size. low frequency operation improves efficiency by reducing mosfet switching losses, both gate charge loss and transition loss. however, lower frequency operation re- quires more inductance for a given amount of ripple current. the ltc1735 uses a constant frequency architecture with the frequency determined by an external oscillator capaci- tor c osc . each time the topside mosfet turns on, the voltage on c osc is reset to ground. during the on-time, c osc is charged by a fixed current. when the voltage on the capacitor reaches 1.19v, c osc is reset to ground. the process then repeats. the value of c osc is calculated from the desired operating frequency assuming no external clock input on the fcb pin: cpf frequency osc () .( ) = ? ? 16110 11 7 a graph for selecting c osc versus frequency is shown in figure 2. the maximum recommended switching fre- quency is 550khz .
12 ltc1735 1735fc the internal oscillator runs at its nominal frequency (f o ) when the fcb pin is pulled high to intv cc or connected to ground. clocking the fcb pin above and below 0.8v will cause the internal oscillator to injection lock to an external clock signal applied to the fcb pin with a frequency between 0.9f o and 1.3f o . the clock high level must exceed 1.3v for at least 0.3 m s and the clock low level must be less than 0.3v for at least 0.3 m s. the top mosfet turn-on will synchronize with the rising edge of the clock. attempting to synchronize to too high an external fre- quency (above 1.3f o ) can result in inadequate slope com- pensation and possible loop instability. if this condition exists simply lower the value of c osc so f ext = f o according to figure 2. applicatio s i for atio wu u u of smaller inductor and capacitor values. so why would anyone ever choose to operate at lower frequencies with larger components? the answer is efficiency. a higher frequency generally results in lower efficiency because of mosfet gate charge losses. in addition to this basic trade off, the effect of inductor value on ripple current and low current operation must also be considered. the inductor value has a direct effect on ripple current. the inductor ripple current d i l decreases with higher induc- tance or frequency and increases with higher v in or v out : d i fl v v v l out out in = ? ? 1 1 ()( ) accepting larger values of d i l allows the use of low inductances, but results in higher output voltage ripple and greater core losses. a reasonable starting point for setting ripple current is d i l = 0.3 to 0.4(i max ). remember, the maximum d i l occurs at the maximum input voltage. the inductor value also has an effect on low current operation. the transition to low current operation begins when the inductor current reaches zero while the bottom mosfet is on. burst mode operation begins when the average inductor current required results in a peak current below 25% of the current limit determined by r sense . lower inductor values (higher d i l ) will cause this to occur at higher load currents, which can cause a dip in efficiency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to decrease. inductor core selection once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot af- ford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy or kool m m ? cores. actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses decrease. unfortunately, increased inductance re- quires more turns of wire and therefore copper losses will increase. figure 2. timing capacitor value operating frequency (khz) 0 100 200 300 400 500 600 c osc value (pf) 1735 f02 100.0 87.5 75.0 62.5 50.0 37.5 25.0 12.5 0 when synchronized to an external clock, burst mode operation is disabled but the inductor current is not allowed to reverse. the 25% minimum inductor current clamp present in burst mode operation is removed, providing constant frequency discontinuous operation over the widest possible output current range. in this mode the synchronous mosfet is forced on once every 10 clock cycles to recharge the bootstrap capacitor. this minimizes audible noise while maintaining reasonably high efficiency. inductor value calculation the operating frequency and inductor selection are inter- related in that higher operating frequencies allow the use kool m m is a registered trademark of magnetics, inc.
13 ltc1735 1735fc ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can con- centrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that induc- tance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! molypermalloy (from magnetics, inc.) is a very good, low loss core material for toroids, but it is more expensive than ferrite. a reasonable compromise from the same manu- facturer is kool m m . toroids are very space efficient, especially when you can use several layers of wire. be- cause they generally lack a bobbin, mounting is more difficult. however, designs for surface mount are available that do not increase the height significantly. power mosfet and d1 selection two external power mosfets must be selected for use with the ltc1735: an n-channel mosfet for the top (main) switch and an n-channel mosfet for the bottom (synchronous) switch. the peak-to-peak gate drive levels are set by the intv cc voltage. this voltage is typically 5.2v during start-up (see extv cc pin connection). consequently, logic-level thresh- old mosfets must be used in most ltc1735 applica- tions. the only exception is when low input voltage is expected (v in < 5v); then, sub-logic level threshold mosfets (v gs(th) < 3v) should be used. pay close attention to the bv dss specification for the mosfets as well; many of the logic level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on resistance r ds(on) , reverse transfer capacitance c rss , input voltage and maximum output current. when the ltc1735 is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: main switch duty cycle v v out in = synchronous switch duty cycle vv v in out in = applicatio s i for atio wu u u the mosfet power dissipations at maximum output current are given by: p v v ir kv i c f main out in max ds on in max rss = () + () + ()( )( )() 2 2 1 d () p vv v ir sync in out in max ds on = () + () () 2 1 d where d is the temperature dependency of r ds(on) and k is a constant inversely related to the gate drive current. both mosfets have i 2 r losses while the topside n-channel equation includes an additional term for transi- tion losses, which are highest at high input voltages. for v in < 20v the high current efficiency generally improves with larger mosfets, while for v in > 20v the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c rss actually provides higher efficiency. the synchronous mosfet losses are greatest at high input voltage or during a short-circuit when the duty cycle in this switch is nearly 100%. the term (1 + d ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but d = 0.005/ c can be used as an approximation for low voltage mosfets. c rss is usually specified in the mosfet characteristics. the constant k = 1.7 can be used to estimate the contributions of the two terms in the main switch dissipation equation. the schottky diode d1 shown in figure 1 conducts during the dead-time between the conduction of the two power mosfets. this prevents the body diode of the bottom mosfet from turning on and storing charge during the dead-time, which could cost as much as 1% in efficiency. a 3a schottky is generally a good size for 10a to 12a regulators due to the relatively small average current. larger diodes can result in additional transition losses due to their larger junction capaci- tance. the diode may be omitted if the efficiency loss can be tolerated.
14 ltc1735 1735fc c in selection in continuous mode, the source current of the top n-channel mosfet is a square wave of duty cycle v out / v in . to prevent large voltage transients, a low esr input capacitor sized for the maximum rms current must be used. the maximum rms capacitor current is given by: ii v v v v rms o max out in in out @ ? ? ? ? () / 1 12 this formula has a maximum at v in = 2v out , where i rms =i o(max) /2. this simple worst case condition is com- monly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. always consult the manufacturer if there is any question. c out selection the selection of c out is primarily determined by the effective series resistance (esr) to minimize voltage ripple. the output ripple ( d v out ) in continuous mode is determined by: dd v i esr fc out l out ?+ ? ? ? ? 1 8 where f = operating frequency, c out = output capaci- tance and d i l = ripple current in the inductor. the output ripple is highest at maximum input voltage since d i l increases with input voltage. typically, once the esr requirement for c out has been met, the rms current rating generally far exceeds the i ripple(pCp) requirement. with d i l = 0.3i out(max) and allowing 2/3 of the ripple due to esr the output ripple will be less than 50mv at max v in assuming: c out required esr < 2.2 r sense c out > 1/(8fr sense ) applicatio s i for atio wu u u the first condition relates to the ripple current into the esr of the output capacitance while the second term guaran- tees that the output capacitance does not significantly discharge during the operating frequency period due to ripple current. the choice of using smaller output capaci- tance increases the ripple voltage due to the discharging term but can be compensated for by using capacitors of very low esr to maintain the ripple voltage at or below 50mv. the i th pin opti-loop compensation compo- nents can be optimized to provide stable, high perfor- mance transient response regardless of the output capaci- tors selected. the selection of output capacitors for cpu or other appli- cations with large load current transients is primarily determined by the voltage tolerance specifications of the load. the resistive component of the capacitor, esr, multiplied by the load current change plus any output voltage ripple must be within the voltage tolerance of the load (cpu). the required esr due to a load current step is: r esr < d v/ d i where d i is the change in current from full load to zero load (or minimum load) and d v is the allowed voltage deviation (not including any droop due to finite capacitance). the amount of capacitance needed is determined by the maximum energy stored in the inductor. the capacitance must be sufficient to absorb the change in inductor current when a high current to low current transition occurs. the opposite load current transition is generally determined by the control loop opti-loop components, so make sure not to over compensate and slow down the response. the minimum capacitance to assure the inductors energy is adequately absorbed is: c li vv out out > () () d d 2 2 where d i is the change in load current. manufacturers such as nichicon, united chemi-con and sanyo can be considered for high performance through- hole capacitors. the os-con semiconductor electrolyte
15 ltc1735 1735fc capacitor available from sanyo has the lowest (esr)(size) product of any aluminum electrolytic at a somewhat higher price. an additional ceramic capacitor in parallel with os-con capacitors is recommended to reduce the inductance effects. in surface mount applications, esr, rms current han- dling and load step specifications may require multiple capacitors in parallel. aluminum electrolytic, dry tantalum and special polymer capacitors are available in surface mount packages. special polymer surface mount capaci- tors offer very low esr but have much lower capacitive density per unit volume than other capacitor types. these capacitors offer a very cost-effective output capacitor solution and are an ideal choice when combined with a controller having high loop bandwidth. tantalum capaci- tors offer the highest capacitance density and are often used as output capacitors for switching regulators having controlled soft-start. several excellent surge-tested choices are the avx tps, avx tpsv or the kemet t510 series of surface mount tantalums, available in case heights rang- ing from 1.5mm to 4.1mm. aluminum electrolytic capaci- tors can be used in cost-driven applications, provided that consideration is given to ripple current ratings, tempera- ture and long-term reliability. a typical application will require several to many aluminum electrolytic capacitors in parallel. a combination of the above mentioned capaci- tors will often result in maximizing performance and minimizing overall cost. other capacitor types include nichicon pl series, nec neocap, panasonic sp and sprague 595d series. consult manufacturers for other specific recommendations. like all components, capacitors are not ideal. each ca- pacitor has its own benefits and limitations. combina- tions of different capacitor types have proven to be a very cost effective solution. remember also to include high frequency decoupling capacitors. they should be placed as close as possible to the power pins of the load. any inductance present in the circuit board traces negates their usefulness. intv cc regulator an internal p-channel low dropout regulator produces the 5.2v supply that powers the drivers and internal circuitry within the ltc1735. the intv cc pin can supply a maxi- mum rms current of 50ma and must be bypassed to ground with a minimum of 4.7 m f tantalum, 10 m f special polymer or low esr type electrolytic capacitor. a 1 m f ceramic capacitor placed directly adjacent to the intv cc and pgnd ic pins is highly recommended. good bypass- ing is required to supply the high transient currents required by the mosfet gate drivers. higher input voltage applications in which large mosfets are being driven at high frequencies may cause the maxi- mum junction temperature rating for the ltc1735 to be exceeded. the system supply current is normally domi- nated by the gate charge current. additional loading of intv cc also needs to be taken into account for the power dissipation calculations. the total intv cc current can be supplied by either the 5.2v internal linear regulator or by the extv cc input pin. when the voltage applied to the extv cc pin is less than 4.7v, all of the intv cc current is supplied by the internal 5.2v linear regulator. power dissipation for the ic in this case is highest: (v in )(i intvcc ) and overall efficiency is lowered. the gate charge is dependent on operating frequency as discussed in the efficiency considerations section. the junction tempera- ture can be estimated by using the equations given in note 2 of the electrical characteristics. for example, the ltc1735cs is limited to less than 17ma from a 30v supply when not using the extv cc pin as follows: t j = 70 c + (17ma)(30v)(110 c/w) = 126 c use of the extv cc input pin reduces the junction tempera- ture to: t j = 70 c + (17ma)(5v)(110 c/w) = 79 c to prevent maximum junction temperature from being exceeded, the input supply current must be checked operating in continuous mode at maximum v in . extv cc connection the ltc1735 contains an internal p-channel mosfet switch connected between the extv cc and intv cc pins. whenever the extv cc pin is above 4.7v, the internal 5.2v regulator shuts off, the switch closes and intv cc power is supplied via extv cc until extv cc drops below 4.5v. this allows the mosfet gate drive and control power to be applicatio s i for atio wu u u
16 ltc1735 1735fc applicatio s i for atio wu u u derived from the output or other external source during normal operation. when the output is out of regulation (start-up, short circuit) power is supplied from the internal regulator. do not apply greater than 7v to the extv cc pin and ensure that extv cc v in . significant efficiency gains can be realized by powering intv cc from the output, since the v in current resulting from the driver and control currents will be scaled by a factor of (duty cycle)/(efficiency). for 5v regulators this simply means connecting the extv cc pin directly to v out . however, for 3.3v and other lower voltage regulators, additional circuitry is required to derive intv cc power from the output. the following list summarizes the four possible connec- tions for extv cc: 1. extv cc left open (or grounded). this will cause intv cc to be powered from the internal 5.2v regulator resulting in an efficiency penalty of up to 10% at high input voltages. 2. extv cc connected directly to v out . this is the normal connection for a 5v output regulator and provides the highest efficiency. for output voltages higher than 5v, extv cc is required to connect to v out so the sense pins absolute maximum ratings are not exceeded. 3. extv cc connected to an output-derived boost network. for 3.3v and other low voltage regulators, efficiency gains can still be realized by connecting extv cc to an output- derived voltage that has been boosted to greater than 4.7v. this can be done with either the inductive boost winding as shown in figure 3a or the capacitive charge pump shown in figure 3b. the charge pump has the advantage of simple magnetics. 4. extv cc connected to an external supply. if an external supply is available in the 5v to 7v range (extv cc v in ), such as notebook main 5v system power, it may be used to power extv cc providing it is compatible with the mosfet gate drive requirements. this is the typical case as the 5v power is almost always present and is derived by another high efficiency regulator. output voltage programming the output voltage is set by an external resistive divider according to the following formula: vv r r out =+ ? ? ? ? 08 1 2 1 . the resistive divider is connected to the output as shown in figure 4 allowing remote voltage sensing. figure 3a. secondary output loop and extv cc connection figure 3b. capacitive charge pump for extv cc extv cc fcb sgnd v in tg sw bg pgnd ltc1735 r sense v out v sec 6.8v + c out + 1 f 1735 f03a n-ch n-ch r4 + c in v in l1 1:n 1n4148 optional extv cc connection 5v v sec 7v r3 extv cc v in tg sw bg pgnd ltc1735 r sense v out vn2222ll + c out 1735 f03b n-ch n-ch + c in + 1 f v in l1 bat85 bat85 bat85 0.22 f
17 ltc1735 1735fc topside mosfet driver supply (c b , d b ) an external bootstrap capacitor c b connected to the boost pin supplies the gate drive voltage for the topside mosfet. capacitor c b in the functional diagram is charged though external diode d b from intv cc when the sw pin is low. note that the voltage across c b is about a diode drop below intv cc . when the topside mosfet is to be turned on, the driver places the c b voltage across the gate-source of the mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage sw rises to v in and the boost pin rises to v in + intv cc . the value of the boost capacitor c b needs to be 100 times greater than the total input capacitance of the topside mosfet. in most applications 0.1 m f to 0.33 m f is ad- equate. the reverse breakdown on d b must be greater than v in(max) . when adjusting the gate drive level, the final arbiter is the total input current for the regulator. if you make a change and the input current decreases, then you improved the efficiency. if there is no change in input current, then there is no change in efficiency. sense + /sense C pins the common mode input range of the current comparator is from 0v to 1.1(intv cc ). continuous linear operation in step-down applications is guaranteed throughout this range allowing output voltages anywhere from 0.8v to 7v. a differential npn input stage is used and is biased with internal resistors from an internal 2.4v source as shown in the functional diagram. this causes current to either be sourced or sunk by the sense pins depending on the output voltage. if the output voltage is below 2.4v current will flow out of both sense pins to the main output. this forces a minimum load current that can be fulfilled by the applicatio s i for atio wu u u figure 4. setting the ltc1735 output voltage v osense sgnd v out r2 1735 f04 ltc1735 r1 47pf v out resistive divider. the maximum current flowing out of the sense pins is: i sense + + i sense C = (2.4v C v out )/24k since v osense is servoed to the 0.8v reference voltage, we can choose r1 in figure 4 to have a maximum value to absorb this current: rk v vv max out 124 08 24 () . . = ? ? ? ? regulating an output voltage of 1.8v, the maximum value of r1 should be 32k. note that at output voltages above 2.4v no maximum value of r1 is necessary to absorb the sense pin currents; however, r1 is still bounded by the v osense feedback current. soft-start/run function the run/ss pin is a multipurpose pin that provides a soft- start function and a means to shut down the ltc1735. soft-start reduces surge currents from v in by gradually increasing the controllers current limit i th(max) . this pin can also be used for power supply sequencing. pulling the run/ss pin below 1.5v puts the ltc1735 into shutdown. this pin can be driven directly from logic as shown in figure 5. the v in quiescent current is a function of run/ss voltage (refer to typical performance charac- teristics graphs on page 6). releasing the run/ss pin allows an internal 1.2 m a current source to charge up the external soft-start capacitor c ss. if run/ss has been pulled all the way to ground there is a delay before starting of approximately: t v a csfc delay ss ss = m =m () 15 12 125 . . ./ when the voltage on run/ss reaches 1.5v the ltc1735 begins operating with a current limit at approximately 25mv/r sense . as the voltage on the run/ss pin increases from 1.5v to 3.0v, the internal current limit is increased from 25mv/r sense to 75mv/r sense . the output current limit ramps up slowly, taking an additional 1.25s/ m f to reach full current. the output current thus ramps up slowly, reducing the starting surge current required from the input power supply.
18 ltc1735 1735fc diode d1 in figure 5 reduces the start delay while allowing c ss to charge up slowly for the soft-start function. this diode and c ss can be deleted if soft-start is not needed. the run/ss pin has an internal 6v zener clamp (see functional diagram). capacitor during a severe overcurrent and/or short-circuit condition. when deriving the 5 m a current from v in as in figure 6a, current latchoff is always defeated. a diode connecting this pull-up resistor to intv cc , as in figure 6b, eliminates any extra supply current during controller shut- down while eliminating the intv cc loading from prevent- ing controller start-up. if the voltage on c ss does not exceed 4.1v, the overcurrent latch is not armed and the function is disabled. why should you defeat overcurrent latchoff? during the prototyping stage of a design, there may be a problem with noise pickup or poor layout causing the protection circuit to latch off. defeating this feature will easily allow trouble- shooting of the circuit and pc layout. the internal short- circuit and foldback current limiting still remains active, thereby protecting the power supply system from failure. after the design is complete, a decision can be made whether to enable the latchoff feature. the value of the soft-start capacitor c ss will need to be scaled with output current, output capacitance and load current characteristics. the minimum soft-start capaci- tance is given by: c ss > (c out )(v out )(10 C4 )(r sense ) the minimum recommended soft-start capacitor of c ss =0.1 m f will be sufficient for most applications. fault conditions: current limit and current foldback the ltc1735 current comparator has a maximum sense voltage of 75mv resulting in a maximum mosfet current of 75mv/r sense . the ltc1735 includes current foldback to help further limit load current when the output is shorted to ground. the foldback circuit is active even when the overload shutdown latch described above is defeated. if the output falls by more than half, then the maximum sense voltage is progressively lowered from 75mv to 30mv. under short-circuit conditions with very low duty cycle, the ltc1735 will begin cycle skipping in order to limit the short-circuit current. in this situation the bottom mosfet will be conducting the peak current. the short-circuit ripple current is determined by the minimum on-time applicatio s i for atio wu u u figure 6. run/ss pin interfacing with latchoff defeated figure 5. run/ss pin interfacing 3.3v or 5v run/ss run/ss d1 c ss c ss 1735 f05 3.3v or 5v run/ss v in intv cc run/ss d1 d1 c ss r ss c ss r ss 1735 f06 (a) (b) fault conditions: overcurrent latchoff the run/ss pin also provides the ability to shut off the controller and latch off when an overcurrent condition is detected. the run/ss capacitor, c ss , is used initially to turn on and limit the inrush current of the controller. after the controller has been started and given adequate time to charge up the output capacitor and provide full load current, c ss is used as a short-circuit timer. if the output voltage falls to less than 70% of its nominal output voltage after c ss reaches 4.1v , the assumption is made that the output is in a severe overcurrent and/or short-circuit condition, so c ss begins discharging. if the condition lasts for a long enough period as determined by the size of c ss , the controller will be shut down until the run/ss pin voltage is recycled. this built-in latchoff can be overridden by providing a current >5 m a at a compliance of 5v to the run/ss pin as shown in figure 6. this current shortens the soft-start period but also prevents net discharge of the run/ss
19 ltc1735 1735fc t on(min) of the ltc1735 (approximately 200ns), the input voltage and inductor value: d i l(sc) = t on(min) v in /l the resulting short-circuit current is: i mv r i sc sense lsc =+ 30 1 2 d () the current foldback function is always active and is not effected by the current latchoff function. fault conditions: output overvoltage protection (crowbar) the output overvoltage crowbar is designed to blow a system fuse in the input lead when the output of the regulator rises much higher than nominal levels. this condition causes huge currents to flow, much greater than in normal operation. this feature is designed to protect against a shorted top mosfet; it does not protect against a failure of the controller itself. the comparator (ov in the functional diagram) detects overvoltage faults greater than 7.5% above the nominal output voltage. when this condition is sensed the top mosfet is turned off and the bottom mosfet is forced on. the bottom mosfet remains on continuously for as long as the 0v condition persists; if v out returns to a safe level, normal operation automatically resumes. note that dynamically changing the output voltage may cause overvoltage protection to be momentarily activated during programmed output voltage decreases. this will not cause permanent latchoff nor will it disrupt the desired voltage change. with soft-latch overvoltage protection, dynamically changing the output voltage is allowed and the overvoltage protection tracks the newly programmed output voltage, always protecting the load. minimum on-time considerations minimum on-time t on(min) is the smallest amount of time that the ltc1735 is capable of turning the top mosfet on and off again. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on- time limit and care should be taken to ensure that: t v vf on min out in () () < if the duty cycle falls below what can be accommodated by the minimum on-time, the ltc1735 will begin to skip cycles. the output voltage will continue to be regulated, but the ripple current and voltage will increase. the minimum on-time for the ltc1735 in a properly configured application is generally less than 200ns. how- ever, as the peak sense voltage decreases, the minimum on-time gradually increases as shown in figure 7. this is of particular concern in forced continuous applications with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with corre- spondingly larger current and voltage ripple. if an application can operate close to the minimum on- time limit, an inductor must be chosen that is low enough to provide sufficient ripple amplitude to meet the mini- mum on-time requirement. as a general rule, keep the inductor ripple current equal or greater than 30% of i out(max) at v in(max) . applicatio s i for atio wu u u ? i l /i out(max) (%) 0 minimum on-time (ns) 100 150 40 1735 f07 50 0 10 20 30 250 200 figure 7. minimum on-time vs d i l
20 ltc1735 1735fc fcb pin operation when the fcb pin drops below its 0.8v threshold, continu- ous mode operation is forced. in this case, the top and bottom mosfets continue to be driven synchronously regardless of the load on the main output. burst mode operation is disabled and current reversal is allowed in the inductor. in addition to providing a logic input to force continuous synchronous operation and external synchronization, the fcb pin provides a means to regulate a flyback winding output (refer to figure 3a). during continuous mode, current flows continuously in the transformer primary. the secondary winding(s) draw current only when the bottom, synchronous switch is on. when primary load currents are low and/or the v in /v out ratio is low, the synchronous switch may not be on for a sufficient amount of time to transfer power from the output capacitor to the secondary load. forced continuous operation will support secondary windings provided there is sufficient synchro- nous switch duty factor. thus, the fcb input pin removes the requirement that power must be drawn from the inductor primary in order to extract power from the auxiliary windings. with the loop in continuous mode, the auxiliary outputs may nominally be loaded without regard to the primary output load. the secondary output voltage v sec is normally set as shown in figure 3a by the turns ratio n of the transformer: v sec @ (n + 1)v out however, if the controller goes into burst mode operation and halts switching due to a light primary load current, then v sec will droop. an external resistive divider from v sec to the fcb pin sets a minimum voltage v sec(min) : vv r r sec min () . ?+ ? ? ? ? 08 1 4 3 if v sec drops below this level, the fcb voltage forces continuous switching operation until v sec is again above its minimum. in order to prevent erratic operation if no external connec- tions are made to the fcb pin, the fcb pin has a 0.17 m a internal current source pulling the pin high. remember to include this current when choosing resistor values r3 and r4. the internal ltc1735 oscillator can be synchronized to an external oscillator by applying and clocking the fcb pin with a signal above 1.5v pCp . when synchronized to an external frequency, burst mode operation is disabled but cycle skipping is allowed at low load currents since current reversal is inhibited. the bottom gate will come on every 10 clock cycles to assure the bootstrap cap is kept re- freshed. the rising edge of an external clock applied to the fcb pin starts a new cycle. the fcb pin must not be driven when the device is in shutdown (run/ss pin low). the range of synchronization is from 0.9f o to 1.3f o , with f o set by c osc . attempting to synchronize to a higher frequency than 1.3f o can result in inadequate slope com- pensation and cause loop instability with high duty cycles (duty cycle > 50%). if loop instability is observed while synchronized, additional slope compensation can be ob- tained by simply decreasing c osc . the following table summarizes the possible states avail- able on the fcb pin: table 1 fcb pin condition dc voltage: 0v to 0.7v burst disabled/forced continuous current reversal enabled dc voltage: 3 0.9v burst mode operation, no current reversal feedback resistors regulating a secondary winding ext clock: (0v to v fcbsync ) burst mode operation disabled (v fcbsync > 1.5v) no current reversal efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: %efficiency = 100% C (l1 + l2 + l3 + ) where l1, l2, etc. are the individual losses as a percentage of input power. applicatio s i for atio wu u u
21 ltc1735 1735fc although all dissipative elements in the circuit produce losses, 4 main sources usually account for most of the losses in ltc1735 circuits: 1) v in current, 2) intv cc current, 3) i 2 r losses, 4) topside mosfet transition losses. 1) the v in current is the dc supply current given in the electrical characteristics which excludes mosfet driver and control currents. v in current results in a small (<0.1%) loss that increases with v in . 2) intv cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from intv cc to ground. the resulting dq/dt is a current out of intv cc that is typically much larger than the control circuit current. in continuous mode, i gatechg = f(q t +q b ), where q t and q b are the gate charges of the topside and bottom-side mosfets. supplying intv cc power through the extv cc switch input from an output-derived or other high efficiency source will scale the v in current required for the driver and control circuits by a factor of (duty cycle)/(efficiency). for ex- ample, in a 20v to 5v application, 10ma of intv cc current results in approximately 3ma of v in current. this reduces the mid-current loss from 10% or more (if the driver was powered directly from v in ) to only a few percent. 3) i 2 r losses are predicted from the dc resistances of the mosfet, inductor and current shunt. in continuous mode the average output current flows through l and r sense , but is chopped between the topside main mosfet and the synchronous mosfet. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l and r sense to obtain i 2 r losses. for example, if each r ds(on) = 0.03 w , r l = 0.05 w and r sense = 0.01 w , then the total resistance is 0.09 w . this results in losses ranging from 2% to 9% as the output current increases from 1a to 5a for a 5v output, or a 3% to 14% loss for a 3.3v output. effeciency varies as the inverse square of v out for the same external components and output power level. i 2 r losses cause the efficiency to drop at high output currents. 4) transition losses apply only to the topside mosfet(s) and only become significant when operating at high input voltages (typically 12v or greater). transition losses can be estimated from: transition loss = (1.7) v in 2 i o(max) c rss f other hidden losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. it is very important to include these system level losses in the design of a system. the internal battery and fuse resis- tance losses can be minimized by making sure that c in has adequate charge storage and very low esr at the switch- ing frequency. a 25w supply will typically require a minimum of 20 m f to 40 m f of capacitance having a maxi- mum of 0.01 w to 0.02 w of esr. other losses including schottky conduction losses during dead-time and induc- tor core losses generally account for less than 2% total additional loss. checking transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out shifts by an amount equal to d i load (esr), where esr is the effective series resis- tance of c out . d i load also begins to charge or discharge c out , generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. opti-loop compensation allows the transient response to be opti- mized over a wide range of output capacitance and esr values. the availability of the i th pin not only allows optimization of control loop behavior but also provides a dc coupled and ac filtered closed loop response test point. the dc step, rise time and settling at this test point truly reflects the closed loop response. assuming a pre- dominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i th external components shown in the figure 1 circuit will provide an adequate starting point for most applications. applicatio s i for atio wu u u
22 ltc1735 1735fc the i th series r c Cc c filter sets the dominant pole-zero loop compensation. the values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop feedback factor gain and phase. an output current pulse of 20% to 100% of full load current having a rise time of 1 m s to 10 m s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. the initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second-order overshoot/dc ratio cannot be used to determine phase margin. the gain of the loop will be increased by increasing r c and the bandwidth of the loop will be increased by decreasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. for a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to applica- tion note 76. a second, more severe transient is caused by switching in loads with large (>1 m f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if the ratio of c load to c out is greater than1:50, the switch rise time should be controlled so that the load rise time is limited to approximately (25)(c load ). thus a 10 m f capacitor would require a 250 m s rise time, limiting the charging current to about 200ma. improve transient response and reduce output capacitance with active voltage positioning fast load transient response, limited board space and low cost are requirements of microprocessor power supplies. applicatio s i for atio wu u u active voltage positioning improves transient response and reduces the output capacitance required to power a microprocessor where a typical load step can be from 0.2a to 15a in 100ns or 15a to 0.2a in 100ns. the voltage at the microprocessor must be held to about 0.1v of nominal in spite of these load current steps. since the control loop cannot respond this fast, the output capacitors must supply the load current until the control loop can respond. capacitor esr and esl primarily determine the amount of droop or overshoot in the output voltage. normally, sev- eral capacitors in parallel are required to meet micropro- cessor transient requirements. active voltage positioning is a form of deregulation. it sets the output voltage high for light loads and low for heavy loads. when load current suddenly increases, the output voltage starts from a level higher than nominal so the output voltage can droop more and stay within the speci- fied voltage range. when load current suddenly decreases the output voltage starts at a level lower than nominal so the output voltage can have more overshoot and stay within the specified voltage range. less output capaci- tance is required when voltage positioning is used be- cause more voltage variation is allowed on the output capacitors. active voltage positioning can be implemented using the opti-loop architecture of the ltc1735 and two resistors connected to the i th pin. an input voltage offset is intro- duced when the error amplifier has to drive a resistive load. this offset is limited to 30mv at the input of the error amplifier. the resulting change in output voltage is the product of input offset and the feedback voltage divider ratio. figure 8 shows a cpu-core-voltage regulator with active voltage positioning. resistors r1 and r4 force the input voltage offset that adjusts the output voltage according to the load current level. to select values for r1 and r4, first determine the amount of output deregulation allowed. the actual specification for a typical microprocessor allows the output to vary 0.112v. the ltc1735 reference accu- racy is 1%. using 1% tolerance resistors, the total feedback divider accuracy is about 1% because both feedback resistors are close to the same value. the result- ing setpoint accuracy is 2% so the output transient
23 ltc1735 1735fc applicatio s i for atio wu u u 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 c osc run/ss i th fcb sgnd v osense sense sense + tg boost sw v in intv cc bg pgnd extv cc u1 ltc1735 c2 0.1 f c8 0.22 f c4 100pf c5 47pf c3 100pf r2 100k r1 27k r5 0.003 gnd v out 1.5v 15a v in 7.5v to 24v gnd c6 1000pf c1 39pf + c10 4.7 f 10v c9 1 f 5v (optional) c11 330pf c19 1 f + c15 to c18 180 f 4v c7 0.1 f m1 fds6680a m2, m3 fds6680a 2 c9, c19: taiyo yuden jmk107bj105 c10: kemet t494a475m010as c12 to c14: taiyo yuden gmk325f106 c15 to c18: panasonic eefue0g181r d1: central semi cmdsh-3 d2: motorola mbrs340 l1: panasonic etqp6f1r0sa m1 to m3: fairchild fds6680a r5: irc lrf2512-01-r003-j u1: linear technology ltc1735cs 1735 f08 d1 cmdsh-3 r6 10k r7 11.5k d2 mbrs340 c12 to c14 10 f 35v l1 1 h r4 100k r3 680k figure 8. cpu-core-voltage regulator with active voltage positioning voltage cannot exceed 0.082v. at v out = 1.5v, the maximum output voltage change controlled by the i th pin would be: d= = = v input offset v v v v mv osense out ref .. . 003 15 08 56 with the optimum resistor values at the i th pin, the output voltage will swing from 1.55v at minimum load to 1.44v at full load. at this output voltage, active voltage position- ing provides an additional 56mv to the allowable tran- sient voltage on the output capacitors, a 68% improve- ment over the 82mv allowed without active voltage positioning. the next step is to calculate the scale factor for v ith , the i th pin voltage. the v ith scale factor reflects the i th pin voltage required for a given load current. v ith controls the peak sense resistor voltage, which represents the dc output current plus one half of the peak-to-peak inductor current. the no load to full load v ith range is from 0.3v to 2.4v, which controls the sense resistor voltage from 0v to the d v sense(max) voltage of 75mv. the calculated v ith scale factor with a 0.003 w sense resistor is: v scale factor v range sense sistor value v vv v va ith ith sense max = d == re (. . ) . . ./ () 24 03 0003 0 075 0 084 v ith at any load current is: vi i v scale factor v offset ith outdc l ith ith =+ d ? ? ? ? ? ? + 2
24 ltc1735 1735fc at full load current: va a va v v ith max pp () . / . . =+ ? ? ? ? ? ? + = - 15 5 2 0 084 0 3 177 at minimum load current: va a va v v ith min pp () ../. . =+ ? ? ? ? ? ? + = - 02 2 2 0 084 0 3 040 in this circuit, v ith changes from 0.40v at light load to 1.77v at full load, a 1.37v change. notice that d i l , the peak-to-peak inductor current, changes from light load to full load. increasing the dc inductor current decreases the permeability of the inductor core material, which de- creases the inductance and increases d i l . the amount of inductance change is a function of the inductor design. to create the 30mv input offset, the gain of the error amplifier must be limited. the desired gain is: a v input offset error v v v ith = d == 137 2003 22 8 . (. ) . connecting a resistor to the output of the transconductance error amplifier will limit the voltage gain. the value of this resistor is: r a error amplifier g ms k ith v m === 22 8 13 17 54 . . . to center the output voltage variation, v ith must be centered so that no i th pin current flows when the output voltage is nominal. v ith(nom) is the average voltage be- tween v ith at maximum output current and minimum output current: v vv v vv vv ith nom ith max ith min ith min () () () () .. .. =+ =+= 2 177 040 2 0 40 1 085 applicatio s i for atio wu u u the thevenin equivalent of the gain limiting resistance value of 17.54k is made up of a resistor r4 that sources current into the i th pin and resistor r1 that sinks current to sgnd. to calculate the resistor values, first determine the ratio between them: k vv v vv v intvcc ith nom ith nom === .. . . () () 52 1085 1 085 379 v intvcc is equal to v extvcc or 5.2v if extv cc is not used. resistor r4 is: rk r k ith 4 1 3 79 1 17 54 84 0 =+ = + = () (. ). . resistor r1 is: r kr k k k ith 1 1 3 79 1 17 54 379 22 17 = + = + = () (. ). . . unfortunately, pcb noise can add to the voltage developed across the sense resistor, r5, causing the i th pin voltage to be slightly higher than calculated for a given output current. the amount of noise is proportional to the output current level. this pcb noise does not present a serious problem but it does change the effective value of r5 so the calculated values of r1 and r4 may need to be adjusted to achieve the required results. since pcb noise is a function of the layout, it will be the same on all boards with the same layout. figures 9 and 10 show the transient response before and after active voltage positioning is implemented. notice that active voltage positioning reduced the transient re- sponse from almost 200mv p-p to a little over 100mv p-p . refer to design solutions 10 for more information about active voltage positioning.
25 ltc1735 1735fc applicatio s i for atio wu u u v in = 12v v out = 1.5v 1.5v 100mv/div 15a 0a 10a/div output voltage load current 50 m s/div 1735 f09 figure 9. normal transient response (without r1, r4) v in = 12v v out = 1.5v 1.582v 1.5v 1.418v 100mv/div 15a 0a 10a/div 50 m s/div 1735 f10 figure 10. transient response with active voltage positioning output voltage load current figure 11. plugging into the cigarette lighter automotive considerations: plugging into the cigarette lighter as battery-powered devices go mobile, there is a natural interest in plugging into the cigarette lighter in order to conserve or even recharge battery packs during operation. but before you connect, be advised: you are plugging into the supply from hell. the main power line in an automobile is the source of a number of nasty potential transients, including load-dump, reverse-battery and double-battery. load-dump is the result of a loose battery cable. when the cable breaks connection, the field collapse in the alternator can cause a positive spike as high as 60v which takes several hundred milliseconds to decay. reverse-battery is just what it says, while double-battery is a consequence of tow-truck operators finding that a 24v jump start cranks cold engines faster than 12v. the network shown in figure 11 is the most straight forward approach to protect a dc/dc converter from the ravages of an automotive power line. the series diode prevents current from flowing during reverse-battery, while the transient suppressor clamps the input voltage during load-dump. note that the transient suppressor should not conduct during double-battery operation, but must still clamp the input voltage below breakdown of the converter. although the ltc1735 has a maximum input voltage of 36v, most applications will be limited to 30v by the mosfet bv dss . v in 50a i pk rating 1735 f11 ltc1735 12v transient voltage suppressor general instrument 1.5ka24a design example as a design example, assume v in = 12v(nominal), v in = 22v(max), v out = 1.8v, i max = 5a and f = 300khz. r sense and c osc can immediately be calculated: r sense = 50mv/5a = 0.01 w c osc = 1.61(10 7 )/(300khz) C 11pf = 43pf assume a 3.3 m h inductor and check the actual value of the ripple current. the following equation is used: d i v fl v v l out out in = ? ? ? ? ()( ) 1 the highest value of the ripple current occurs at the maximum input voltage: d i v khz h v v a l = m ? ? ? ? = 18 300 3 3 1 18 22 17 . (. ) . . the maximum ripple current is 33% of maximum output current, which is about right. figure 8 circuit figure 8 circuit
26 ltc1735 1735fc applicatio s i for atio wu u u next verify the minimum on-time of 200ns is not violated. the minimum on-time occurs at maximum v in : t v vf v v khz ns on min out in max () () . () == = 18 22 300 273 since the output voltage is below 2.4v the output resistive divider will need to be sized to not only set the output voltage but also to absorb the sense pin current. rk v vv k v vv k max out 124 08 24 24 08 24 18 32 () . . . .. = ? ? ? ? = ? ? ? ? = choosing 1% resistors: r1 = 25.5k and r2 = 32.4k yields an output voltage of 1.816v. the power dissipation on the topside mosfet can be easily estimated. choosing a siliconix si4412ady results in r ds(on) = 0.035 w , c rss = 100pf. at maximum input voltage with t(estimated) = 50 c: p v v cc v a pf khz mw main = () + [] w () + ()()( )( ) = 18 22 5 1 0 005 50 25 0 035 1 7 22 5 100 300 204 2 2 . ( . )( ) . . because the duty cycle of the bottom mosfet is much greater than the top, a larger mosfet, siliconix si4410dy, (r ds(on) = 0.02 w ) is chosen. the power dissipation in the bottom mosfet, again assuming t a = 50 c, is: p vv v a mw sync = ()() w () = 22 1 8 22 511002 505 2 . .. thanks to current foldback, the bottom mosfet dissipa- tion in short-circuit will be less than under full load conditions. c in is chosen for an rms current rating of at least 2.5a at temperature. c out is chosen with an esr of 0.02 w for low output ripple. the output ripple in continuous mode will be highest at the maximum input voltage. the worst-case output voltage ripple due to esr is approximately: vri amv oripple esr l p p ==w= - (). (.) d 002 23 46 pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc1735. these items are also illustrated graphically in the layout diagram of figure 12. check the following in your layout: 1) are the signal and power grounds segregated? the ltc1735 pgnd pin should tie to the ground plane close to the input capacitor(s). the sgnd pin should then connect to pgnd, and all components that connect to sgnd should make a single point tie to the sgnd pin. the synchronous mosfet source pins should connect to the input capacitor(s) ground. 2) does the v osense pin connect directly to the feedback resistors? the resistive divider r1, r2 must be connected between the (+) plate of c out and signal ground. the 47pf to 100pf capacitor should be as close as possible to the ltc1735. be careful locating the feedback resistors too far away from the ltc1735. the v osense line should not be routed close to any other nodes with high slew rates. 3) are the sense C and sense + leads routed together with minimum pc trace spacing? the filter capacitor between sense + and sense C should be as close as possible to the ltc1735. ensure accurate current sensing with kelvin connections as shown in figure 13. series resistance can be added to the sense lines to increase noise rejection. 4) does the (+) terminal of c in connect to the drain of the topside mosfet(s) as closely as possible? this capacitor provides the ac current to the mosfet(s). 5) is the intv cc decoupling capacitor connected closely between intv cc and the power ground pin? this capaci- tor carries the mosfet driver peak currents. an addi- tional 1 m f ceramic capacitor placed immediately next to
27 ltc1735 1735fc applicatio s i for atio wu u u figure 12. ltc1735 layout diagram figure 13. kelvin sensing r sense the intv cc and pgnd pins can help improve noise performance. 6) keep the switching node (sw), top gate node (tg) and boost node (boost) away from sensitive small-signal nodes, especially from the voltage and current sensing 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 c osc run/ss i th fcb sgnd v osense sense sense + tg boost sw v in intv cc bg pgnd extv cc ltc1735 c ss c c2 c c r c 47pf 1000pf + c out c osc r1 r2 c b d b r sense d1 m2 + 4.7 f m1 + c in + l1 v in + v out 1735 f12 sense + sense high current path 1735 f13 current sense resistor (r sense ) feedback pins. all of these nodes have very large and fast moving signals and therefore should be kept on the output side (pin 9 to pin 16) of the ltc1735 and occupy minimum pc trace area.
28 ltc1735 1735fc typical applicatio s u 1.8v/5a converter from design example with burst mode operation disabled 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 c osc run/ss i th fcb sgnd v osense sense sense + tg boost sw v in intv cc bg pgnd extv cc ltc1735 c ss 0.1 f c b 0.1 f c c2 220pf 47pf c c 470pf r c 33k r sense 0.01 v out 1.8v 5a 1000pf c osc 43pf + 4.7 f + c out 150 f 6.3v 2 panasonic sp c in 22 f 50v cer m1 si4412dy m2 si4410dy c out : panasonic eefueog151r c in : marcon thcr70le1h226zt l1: panasonic etqp6f3r3hfa r sense : irc lr 2010-01-r010f 1735 ta02 d b cmdsh-3 r2 32.4k 1% r1 25.5k 1% mbrs140t3 v in 4.5v to 22v l1 3.3 h optional: connect to 5v sgnd cpu core voltage regulator for 2-step applications (v in = 5v) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 c osc run/ss i th fcb sgnd v osense sense sense + tg boost sw v in intv cc bg pgnd extv cc ltc1735 c ss 0.1 f c b 0.22 f c c2 220pf 47pf c c 220pf r c 20k 100k* *optional to defeat overcurrent latchoff r sense 0.004 v out 1.5v 12a 1000pf c osc 39pf + 4.7 f 1 f 100pf + + c out 180 f 4v 3 c o 47 f 10v c in 150 f 6.3v 2 m1 fds6680a m2, m3 fds6680a 2 c out : panasonic eefueog181r c in : panasonic eefueoj151r c o : taiyo yuden lmk550bj476mm-b l1: coilcraft 1705022p-781hc r sense : irc lrf 2512-01-r004-j 1735 ta03 d b mbr0530 r2 22.6k 1% r1 25.5k 1% mbrd835l v in 5v l1 0.78 h v in sgnd
29 ltc1735 1735fc typical applicatio s u selectable output voltage converter with burst mode operation disabled for cpu power 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 nc c osc run/ss i th fcb sgnd v osense pgood sense sense + nc tg boost sw v in intv cc bg pgnd extv cc nc ltc1735f c ss 0.1 f c b 0.22 f 0.1 f 4.7 c c2 47pf 47pf c c 330pf r c 33k r sense 0.004 v out 1.35v/1.60v 12a 1000pf c osc 43pf + 4.7 f 1 f cer + c out 470 f 6.3v 3 kemet on: v out = 1.60v off: v out = 1.35v c in : marcon thcr70eih226zt c out : kemet t510x447m006as l1: panasonic etqp6f1r2hfa r sense : irc lrf2512-01-r004f m1 fds6680a m2 fds6680a 2 1735 ta05 c in 22 f 2 cer d b cmdsh-3 r2 10k 1% r1 14.3k 1% 47pf 47pf 10k mbrs340t3 v in 4.5v to 24v l1 1.2 h optional: connect to 5v nc nc nc power good r3 33.2k 1% sgnd vn2222 10 10 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 c osc run/ss i th fcb sgnd v osense sense sense + tg boost sw v in intv cc bg pgnd extv cc ltc1735 c ss 0.1 f c c2 100pf c c 2200pf r c 3.3k 1m v out 10k 6.2v fmmt625 r sense 0.004 22 t1 v in 4v to 40v 6 7 10 3 47 r2 113k 1% c out 220 f 16v 4 v out 12v 3a r1 8.06k 1% 3300pf 47pf c osc 150pf + 4.7 f 0.1 f c in : marcon thcr70eih226zt c out : avx tpsv227m016r0150 t1: coiltronics vp5-0155 r sense : irc lrf2512-01-r004f m1 irl2910s m2 si4850ey mbrs1100 1735 ta07 + 100 1nf 100v 1nf 100v c in 22 f 50v 2 cmdsh-3 4v to 40v input to 12v flyback converter
30 ltc1735 1735fc dual output 15w 3.3v/5v power supply typical applicatio s u 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 c osc run/ss i th fcb sgnd v osense sense sense + tg boost sw v in intv cc bg pgnd extv cc ltc1735 c ss 0.1 f c b 0.1 f c c2 220pf 100pf c c 470pf r c 33k r sense 0.012 v out 5v 3.5a v out2 12v 120ma unreg 1000pf c osc 51pf + 4.7 f + c out 100 f 10v 3 avx + c sec 22 f 35v avx m1 si4802dy m2 si4802dy 1735 ta04 + c in 22 f 30v os-con d b cmdsh-3 r2 105k 1% c in : sanyo os-con 30sc22m c out : avx tpsd107m010r0068 t1: 1:8 dale lpe6562-a262 r1 20k 1% mbrs140t3 v in 5.5v to 28v t1 1:1.8 10 h sgnd mbrs1100t3 22 1000pf 10k 100 100 140k 5v/3.5a converter with 12v/200ma auxiliary output 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 c osc run/ss i th fcb sgnd v osense sense sense + tg boost sw v in intv cc bg pgnd extv cc ltc1735 c ss 0.1 f c b 0.1 f 0.01 f c c2 100pf 100pf c c 470pf r c 33k r sense 0.01 v out1 3.3v 2.5a 1000pf c osc 47pf + 4.7 f + c out1 100 f 10v 2 c out2 100 f 10v 2 v out2 5v 1.5a m1 si4412dy m2 si4412dy m3 si4412dy 1735 ta08 c in 22 f 50v d b cmdsh-3 r2 62.6k 1% c in : marcon thcr70eih226zt c out1, 2 : avx tpsd107m010r0065 t1: bi technologies hm00-93839 r sense : irc lrf2512-01-r010 f r1 20k 1% mbrs140t3 cmdsh-3 mbrs140t3 v in 4.5v to 28v t1a t1b t1c 4.7k 18 v out2 27 36 sgnd +
31 ltc1735 1735fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. s package 16-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) package descriptio n u gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) f package 20-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1650) f20 tssop 0502 0.09 ?0.20 (.0036 ?.0079) 0 ?8 0.45 ?0.75 (.018 ?.030) 4.30 ?4.50** (.169 ?.177) 1.10 (.0433) max 0.05 ?0.15 (.002 ?.006) 0.65 (.0256) bsc 0.195 ?0.30 (.0077 ?.0118) 6.40 bsc 134 5 6 7 8910 11 12 14 13 6.40 ?6.60* (.252 ?.260) 20 19 18 17 16 15 2 millimeters (inches) dimensions do not include mold flash. mold flash shall not exceed .152mm (.006") per side dimensions do not include interlead flash. interlead flash shall not exceed .254mm (.010") per side * ** note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale recommended solder pad layout 0.45 0.05 0.65 typ 4.50 0.10 6.60 0.10 1.05 0.10 gn16 (ssop) 0502 .016 ?.050 (0.406 ?1.270) .015 .004 (0.38 0.10) 45 0 ?8 typ .007 ?.0098 (0.178 ?0.249) .053 ?.068 (1.351 ?1.727) .008 ?.012 (0.203 ?0.305) .004 ?.0098 (0.102 ?0.249) .0250 (0.635) bsc 12 3 4 5 6 7 8 .229 ?.244 (5.817 ?6.198) .150 ?.157** (3.810 ?3.988) 16 15 14 13 .189 ?.196* (4.801 ?4.978) 12 11 10 9 .009 (0.229) ref .254 min recommended solder pad layout .150 ?.165 .0250 typ .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale .016 ?.050 (0.406 ?1.270) .010 ?.020 (0.254 ?0.508) 45 0 ?8 typ .008 ?.010 (0.203 ?0.254) 1 n 2 3 4 5 6 7 8 n/2 .150 ?.157 (3.810 ?3.988) note 3 16 15 14 13 .386 ?.394 (9.804 ?10.008) note 3 .228 ?.244 (5.791 ?6.197) 12 11 10 9 s16 0502 .053 ?.069 (1.346 ?1.752) .014 ?.019 (0.355 ?0.483) typ .004 ?.010 (0.101 ?0.254) .050 (1.270) bsc .245 min n 123 n/2 .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm)
32 ltc1735 1735fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com ? linear technology corporation 1998 lt/tp 0104 rev c 1k ? printed in usa typical applicatio u 3.3v to 2.5v/5a converter with external clock synchronization operating at 500khz 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 c osc run/ss i th fcb sgnd v osense sense sense + tg boost sw v in intv cc bg pgnd extv cc ltc1735 c ss 0.1 f c b 0.1 f 0.1 f c c2 51pf 47pf c c 330pf r c 33k r sense 0.01 v out 2.5v 5a 1000pf c osc 20pf + 4.7 f + c out 100 f 10v avx 3 m1 si4410dy m2 si4410dy 47pf 1735 ta06 + c in 100 f 10v os-con d b cmdsh-3 r2 43.2k 1% c in : sanyo os-con 10sl100m c out : avx tpsd107m010r0065 l1: coilcraft do3316p-152 r sense : irc lr2010-01-r010-f r1 20k 1% mbrs140t3 v in 3.3v 5v l1 1.5 h sgnd ext clock 500khz part number description comments ltc1530 high power step-down synchronous dc/dc controller high efficiency 5v to 3.3v conversion at up to 15a in so-8 ltc1628/ltc3728 2-phase, dual output synchronous step-down reduces c in and c out , power good output signal, synchronizable, dc/dc controllers 3.5v v in 36v, i out up to 20a, 0.8v v out 5v ltc1629/ltc3729 20a to 200a polyphase synchronous controllers expandable from 2-phase to 12-phase, uses all surface mount components, no heat sink, v in up to 36v ltc1702 no r sense tm 2-phase dual synchronous step-down 550khz, no sense resistor controller ltc1708-pg 2-phase, dual synchronous controller with mobile vid 3.5v v in 36v, vid sets v out1 , pgood ltc1736 high efficiency synchronous controller with 5-bit mobile output fault protection, 24-pin ssop, vid control 3.5v v in 36v ltc1778 no r sense current mode synchronous step-down up to 97% efficiency, 4v v in 36v, 0.8v v out (0.9)(v in ), controller i out up to 20a ltc1929/ 2-phase synchronous controllers up to 42a, uses all surface mount components, ltc1929-pg no heat sinks, 3.5v v in 36v ltc3711 no r sense current mode synchronous step-down up to 97% efficiency, ideal for pentium ? iii processors, controller with digital 5-bit interface 0.925v v out 2v, 4v v in 36v, i out up to 20a ltc3729 20a to 200a, 550khz polyphase synchronous controller expandable from 2-phase to 12-phase, uses all surface mount components, v in up to 36v ltc3730 imvp iii 3-phase synchronous controller i out up to 60a, 0.6v v out 1.75v, integrated mosfet drivers ltc3732 vrm 9.0/9.1 3-phase dc/dc synchronous step-down 1.1v v out 1.85v, 4.5v v in 32v, ssop-36 controller ltc3778 optional r sense current mode synchronous step-down 4v v in 36v, adjustable frequency up to 1.2mhz, tssop-20 controller LTC3832 low v in high power synchronous controller v out 3 0.6v, i out 20a, 3v v in 8v ltc4008 4a multichemistry multicell battery charger nicd, nimh, lead acid, li-ion batteries; 6v v in 28v; 1.19v v out 28v no r sense is a trademark of linear technology corporation. pentium is a registered trademark of intel corporation. related parts

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